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up8809 1 up8809-ds-f0000, jan. 2015 www.upi-semi.com 2a ultra low dropout linear regulator the up8809 is an ultra low dropout linear regulator specifically designed to provide termination voltage for ddr memory system. designed with low on-resistance nmosfets, this device is capable of sinking/sourcing up to 2a output current. this device works with dual supplies, a control input for the control circuitry and a power input as low as 1.0v for providing current to output. the output voltage is tightly regulated to track reference voltage input within 20mv variation with fast to line/load transient. other features include chip shutdown function, soft-start, on-chip thermal protection, and bi-directional current limit protection. the up8809 is available in psop-8l, fsop- 8l, wdfn3x3-8l packages with very low thermal resistance. ? ? ? ? ? desktop pcs, notebooks, and workstations ? ? ? ? ? graphic cards ? ? ? ? ? low voltage logic supplies ? ? ? ? ? microprocessor and chipset supplies ? ? ? ? ? split plane microprocessor supplies ? ? ? ? ? advanced graphics cards supplies ? ? ? ? ? soundcards and auxiliary power supplies ? ? ? ? ? smps post regulators ? ? ? ? ? generate termination voltage for ddr memory interface ? ? ? ? ? output voltage traces reference input ? ? ? ? ? capable of sinking/sourcing 2a ? ? ? ? ? integrated low r ds(on) mosfets ? ? ? ? ? excellent line and load regulation ? ? ? ? ? low external part count ? ? ? ? ? bidirectional current limit protection ? ? ? ? ? on-chip thermal protection ? ? ? ? ? support pure mlcc ? ? ? ? ? rohs compliant and halogen free general description applications ordering information features pin configuration & typical application circuit r e b m u n r e d r oe p y t e g a k c a pg n i k r a m p o t 8 w s p 9 0 8 8 p ul 8 - p o s pp 9 0 8 8 p u 8 f s p 9 0 8 8 p ul 8 - p o s fp 9 0 8 8 p u 8 d d p 9 0 8 8 p ul 8 - 3 x 3 n f d wp 9 0 8 8 p u : s u t a t s 8 w s p 9 0 8 8 p u : n o i t c u d o r p n i y t i l i b a l i a v a n o i t c u d o r p / e l p m a s e h t k c e h c e s a e l p : s r e h t o . s e v i t a t n e s e r p e r i p u h t i w note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirement. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. 4 3 2 18 7 6 pgnd vcnt l nc gnd nc refin 5nc vout wdfn3x3 C 8l vin vcnt l nc nc vin nc gnd refin vout gnd 1 2 3 45 6 7 8 psop C 8l vcntl vin gnd refin vout 1 2 3 45 6 7 8 fsop C 8l vcntl vcntl vcntl 5vcc v in vout vin vcntl c out r dummy r1 gnd r3 r2 c ss c cntl c in en refin
up8809 2 up8809-ds-f0000, jan. 2015 www.upi-semi.com . o ne m a nn o i t c n u f n i p 1n i v . e g a t l o v t u p n i e h t o t t n e r r u c s e i l p p u s t a h t e c i v e d r e w o p e h t o t t u p n i n i a r d e h t s i s i h t s i h t o t e s o l c y l l a c i s y h p d e c a l p e b d l u o h s r s e w o l h t i w s r o t i c a p a c k l u b e g r a l . n i p t u p t u o c i m a r e c f u 0 1 a . t n e i s n a r t d a o l e g r a l g n i r u d g n i p p o r d m o r f l i a r t u p n i e h t t n e v e r p o t n i p v . n i p s i h t t a d e d n e m m o c e r s i r o t i c a p a c n i v n a h t r e h g i h d e c r o f e b t o n n a c l t n c e s i w r e h t o . e g a t l o v t u p t u o e h t e l b a s i d d n a d e r e g g i r t e s l a f e b y a m n o i t c n u f t i m i l t n e r r u c e h t 2d n g . d n u o r g 3n i f e r . t u p n i e g a t l o v e c n e r e f e r e h t . r e i f i l p m a r o r r e e h t f o t u p n i g n i t r e v n i - n o n e h t s i n i p s i h t d e r o t i n o m o s l a s i n i p s i h t . t u p n i e g a t l o v e c n e r e f e r e h t k c a r t o t d e t a l u g e r s i e g a t l o v t u p t u o . e c i v e d s i h t n w o d s t u h s v 5 1 . 0 n a h t r e w o l n i p s i h t g n i l l u p . r o t a r a p m o c n w o d t u h s e h t y b 4t u o v . e g a t l o v t u p t u o n e h w s t s i x e e c n a t s i s e r w o l l l u p a . e c i v e d e h t f o t u p t u o r e w o p s i n i p s i h t e s n o p s e r t n e i s n a r t e t a u q e d a n i a t n i a m o t . n i p n e e h t w o l g n i l l u p y b d e l b a s i d s i e c i v e d e h t c i m a r e c f u 0 1 h t i w r o t i c a p a c c i t y l o r t c e l e l a f u 0 0 0 1 f o e u l a v l a c i p y t , e g n a h c d a o l e g r a l o t . t u o v n o s t n e i s n a r t t n e r r u c f o s t c e f f e e h t e c u d e r o t d e d n e m m o c e r e r a s r o t i c a p a c 8 , 7 , 5c n . d e t c e n n o c y l l a n r e t n i t o n 6l t n c v . t i u c r i c l o r t n o c r o f t u p n i y l p p u s y r t i u c r i c l o r t n o c e h t o t e g a t l o v s a i b s e d i v o r p n i p s i h t d e n o i t r o p o r p s i t n e r r u c t u p t u o f o y t i l i b a p a c g n i v i r d e h t . r o t s i s n a r t s s a p e h t r o f r e v i r d d n a v e h t o t l t n c v v 0 . 2 t s a e l t a e b t s u m n i p s i h t n o e g a t l o v e h t , e t a l u g e r o t e c i v e d e h t r o f . v n a h t s s e l o n d n a , e g a t l o v t u p t u o e h t n a h t r e t a e r g . n i m _ l t n c v l t n c e b t s u m e g a t l o v t u p n i v e r o f e b y d a e r n i . e g a t l o v t u p n i d a p d e s o p x ed n g . d n u o r g e b d l u o h s d n a h t a p n o i t a p i s s i d r e w o p t n a n i m o d e h t s t c a d a p d e s o p x e e h t e h t n i d e b i r c s e d s a s d a p b c p n g i s e d l l e w o t d e r e d l o s . r e t p a h c s n o i t a m r o f n i n o i t a c i l p p a functional pin description functional block diagram shutdown current limit thermal protection cntl vin vout gnd refin 0.4v chip enable error amplifier
up8809 3 up8809-ds-f0000, jan. 2015 www.upi-semi.com definitions some important terminologies for ldo are specified below. dropout voltage the input/output voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. measured when the output drops 2% below its nominal value. dropout voltage is affected by junction temperature, load current and minimum input supply requirements. line regulation the change in output voltage for a change in input voltage. the measurement is made under the conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. load regulation the change in output voltage for a change in load current at constant chip temperature. the measurement is made under the conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. maximum power dissipation the maximum total device dissipation for which the regulator will operate within specifications. quiescent bias current current which is used to operate the regulator chip and is not delivered to the load. the quiescent current i q is defined as the supply current used by the regulator itself that does not pass into the load. it typically includes all bias currents required by the ldo and any drive current for the pass transistor. general the up8809 is an ultra low dropout linear regulator specifically designed to provide termination voltage for ddr memory system. designed with low on-resistance nmosfets, this device is capable of sinking/sourcing up to 2a output current. this device works with dual supplies, a control input for the control circuitry and a power input as low as 1.0v for providing current to output. the output voltage is tightly regulated to track reference voltage input within 20mv variation with fast to line/load transient. other features include chip shutdown function, soft-start, on-chip thermal protection, and bi-directional current limit protection. power on reset the up8809 mainly consists of power on reset and chip enable, pass transistors, current limit, error amplifier and functional description temperature protection as shown in functional block diagram . the up8809 continuously monitors control input and power input for power on reset (por) to ensure the device can work properly. the typical por rising levels are 2.7v and 0.6v for control input and power input respectively. chip enable and soft start once por is granted, the up8809 is ready for normal operation. the refin pin is a dual-function input pin: reference input and shutdown control input. a singal level transistor is adequate to pull this pin lower than 0.15v and shuts down the device reducing the shutdown current below 50ua. the up8809 tightly regulates the output voltage to track v refin if it is higher than 0.4v. the output voltage ramp up/ down speed is limited as 5.7mv/us to limit inrusht current form power input as shown in figure 1. the inrush current to charge/discharge the output capacitor is calculated as: i inrush = 5.7mv/us x c out v out (500mv/div) i vin (2a/div) refin (500mv/div) figure 1. chip enable and soft start a 100uf output capacitor will demand 0.5v input current during softstart. if the output capacitor is larger than 470uf, current limit function may be activated and limit the inrush current to about 2.2a. make sure the power input is capable of delivering inrush current with selected output capacitor. output voltage regulation the output voltage is tightly regulated to track the reference voltage applied at refin pin. the error signal is amplified to control the gates of nmosfet for sourcing current from vin and singing current gnd respectively. since the gate voltage is provided by the control input v cntl , it is highly recommended the control input is 2v higher than the output voltage to achieve tight regulation and fast transient response. time: 100us/div v in = 2.5v, v cntl = 5v, c out = 470uf
up8809 4 up8809-ds-f0000, jan. 2015 www.upi-semi.com current limit the up8809 monitors sourcing and sinking ouput currents. the output currents are limited to a safe level by reducing the gate voltages of the nmosfet during output overload or short circuit. the output voltage is reduced if the load continuously demands current higher than the current limit level. the output voltage is re-built up when overload or short circuit conditions are removed. i out (2a/div) v out (500mv/div) figure 1. vout output source current limit i out (2a/div) v out (1v/div) figure 2. vout output sink current limit functional description thermal protection the up8809 implements a thermal shutdown function to protect the device from damage when output overload or short circuit. both nmosfets are turned off when the juction temperature exceeds about 170 o c, allowing the junction temperature to cool down. the output voltage is re-built up when the junction temperature reduces by 40 o c, resulting in a pulsed output during continuous thermal over load conditions. the thermal protection is designed to protect the device from damage during abnormal operation. it is highly recommended to keep the maximum junction temperature under 150 o c during normal operation for maximum realiability. time: 2ms/div v in = 2.5v, v cntl = 5v, c out = 1.25v time: 2ms/div v in = 2.5v, v cntl = 5v, c out = 1.25v
up8809 5 up8809-ds-f0000, jan. 2015 www.upi-semi.com (note 1) control input voltage v cntl ------------------------------------------------------------------------------------------------------------- -0.3v to +7v power input voltage v in -------------------------------------------------------------------------------------------------------------------- -0.3v to +7v other pins --------------------------------------------------------------------------------------------------------------- -0. 3v to (v cntl + 0.3v) storage temperature range ----------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 200v package thermal resistance (note 3) psop-8l ja ------------------------------------------------------------------------------------------------------------------------------ 50 o c/w psop-8l jc ------------------------------------------------------------------------------------------------------------------------------ - 5 o c/w fsop-8l ja ------------------------------------------------------------------------------------------------------------------------------ 90 o c/w fsop-8l jc ------------------------------------------------------------------------------------------------------------------------------ 35 o c/w wdfn3x3-8l ja -------------------------------------------------------------------------------------------------------------------------- 60 o c/w wdfn3x3-8l jc --------------------------------------------------------------------------------------------------------------------------- 5 o c/w power dissipation, p d @ t a = 25 o c psop-8l ----------------------------------------------------------------------------------------------------------------------- -------------------- 2.0w fsop-8l ------------------------------------------------------------------------------------------------------------------------------ --- 1.11w wdfn3x3-8l ------------------------------------------------------------------------------------------------------------------------------ -------- 1.67w (note 2) operating junction temperature ra nge ------------------------------------------------------------------------------------ -40 o c to +125 o c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 o c to +85 o c supply input voltage, v cntl ------------------------------------------------------------------------------------------------------------ +2.8v to +6.0v power input voltage, v in ------------------------------------------------------------------------------------------------------------ +1.0v to v cntl absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
up8809 6 up8809-ds-f0000, jan. 2015 www.upi-semi.com r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u e g a t l o v t u p n i y l p p u s d l o h s e r h t r o pv h t r l t n c v l t n c g n i s i r- -7 . 28 . 2v s i s e r e t s y h r o pv s y h l t n c v l t n c g n i l l a f- -2 . 0- -v n w o d t u h s n i t n e r r u c t u p n i l o r t n o ci d s _ l t n c v l t n c v = n i i , v 0 . 5 = t u o v , a 0 = n i f e r v 0 =- -0 50 9a u t n e r r u c t u p n i l o r t n o ci l t n c v l t n c v , v 0 . 5 = n i v , v 8 . 1 = n i f e r , v 9 . 0 = i t u o . a 0 = - -5 . 05 . 1a m e g a t l o v t u p t u o t e s f f o e g a t l o v t u p t u ov s o v l t n c v , v 0 . 5 = n i v , v 8 . 1 = n i f e r , v 9 . 0 = i t u o . a 0 = 0 2 -- -0 2 +v m n o i t a l u g e r d a o l ? v d a o l i < a 1 - t u o a 1 <0 2 -- -0 2 +v m e g a t l o v t u o p o r dv t u o p o r d v l t n c i , v 5 . 4 = t u o = t u o v , a 5 . 1 = v 5 2 . 1 - -5 2 25 2 5v m v l t n c i , v 5 . 4 = t u o = t u o v , a 0 . 1 = v 5 2 . 1 - -0 5 10 5 3v m n o i t c e t o r p t i m i l t n e r r u c i _ t i m i le c r u o s v n i v , v 8 . 1 = t u o g n i c r u o s , v 9 . 0 =3 . 2- -- - a i _ t i m i lk n i s v n i v , v 8 . 1 = t u o g n i k n i s , v 9 . 0 =2- -- - t i u c r i c t r o h s i n i v _ c s g n i k n i s , n i v o t t i u c r i c t r o h s t u o v1- -- -a i d n g _ c s g n i c r u o s , d n g o t t i u c r i c t r o h s t u o v5 . 1- -- -a n w o d t u h s / e l b a n e n i f e r d l o h s e r h t h g i h c i g o l n i f e rv h n e e c i v e d e h t e l b a n e o t g n i s i r n i f e r4 . 0- -- -v d l o h s e r h t w o l c i g o l n i f e rv l n e e c i v e d e h t e l b a s i d o t g n i l l a f n i f e r- -- -5 1 . 0v n o i t c e t o r p l a m r e h t e r u t a r e p m e t n w o d t u h s l a m r e h tt d s - -0 6 1- - o c s i s e r e t s y h n w o d t u h s l a m r e h tt s y h d s - -0 3- - o c electrical characteristics (v cntl = 5v, t a = 25 o c, unless otherwise specified)
up8809 7 up8809-ds-f0000, jan. 2015 www.upi-semi.com v out (500mv/div) i vin (2a/div) refin (500mv/div) v out (500mv/div) i in (2a/div) v cntl (2v/div) -20mv 0mv 20mv 0a 1a 2a -1a -2a sourcing 10mv -10mv sinking v out (20mv/div) i out (2a/div) v refin (1v/div) v out (1v/div) v out (0.5v/div) v refin (0.5v/div) v in (1v/div) typical operation characteristics power on from v in time: 2ms/div v cntl = 5v, v refin = 1.25v, c out = 470uf power on from v cntl time: 100us/div v in = 2.5v, v refin = 1.25v, c out = 470uf trun on from refin time: 100us/div v in = 2.5v, v cntl = 5v, c out = 470uf refin step change time: 200us/div v in = 2.5v, v cntl = 5v, c out = 1000uf load regulation output current (a) v out - v refin (mv) load transient response time: 100us/div v in = 2.5v, v cntl = 5v, c out = 1000uf
up8809 8 up8809-ds-f0000, jan. 2015 www.upi-semi.com 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 2 2.5 3 3.5 4 4.5 5 5.5 6 0 100 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 typical operation characteristics shutdown current vs. input voltage input voltage v in = v cntl (v) shutdown current (ua) quiescent current vs. input voltage input voltage v in = v cntl (v) quiescent current (ua) shutdown current vs. temperature junction temperature ( o c) shutdown current (ua) quiescent current vs. temperature junction temperature ( o c) quiescent current (ua) on resistance vs. temperature junction temperature ( o c) vcntl = 5.0v, for both sink and source on resistance (m ? )
up8809 9 up8809-ds-f0000, jan. 2015 www.upi-semi.com application information the up8809 is an ultra low dropout linear regulator specifically designed to provide termination voltage for ddr memory system. designed with low on-resistance nmosfets, this device is capable of sinking/sourcing up to 2a output current. the output voltage is tightly regulated to track reference voltage input within 20mv variation with fast to line/load transient. supply voltage for control circuit v cntl this up8809 works with dual supplies, a control input for the control circuitry and a power input as low as 1.0v for providing current to output. the control input provides bias current for control circuit and gate voltage for turning on and off the nmosfets. it is highly recommended to keep the control input 2.0v higher than the output voltage for optimal performance. connect vcntl pin to a 5v voltage source when available. the control voltage should be locally bypassed by a minimum 1uf ceramic capacitor plus a 10 ? resistor. power input v in and input capacitor c cntl , c in the vin pin supplies current to output when the upper mosfet turns on. the up8809 is designed to work with minimum 10uf ceramic input capacitor. however, a bulk capacitor is still recommended in parallel with the ceramic capacitor to stabalize the input voltage during output soft start and load transient. since both power and control inputs are independently monitored for power on reset, special power sequence concern is not required for control input and power input. when work with large output capacitor, the up8809 may demand large input current during soft start. make sure the power input is capable of delevering up to 3a. t n e n o p m o ce u l a v d e d n e m m o c e r c l t n c c / n i c i m a r e c f u 0 1 / f u 1 m u m i n i m r o t i c a p a c note: a low-esr 1uf/10uf capacitor with minimal susceptibility to temperature is recommended, and stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. the c in total capacitance of input capacitors value including ceramic and aluminum electrolytic capacitors should be larger than 10uf. a 1uf ceramic capacitor (c cntl ) or higher is recommended for noise decoupling. reference input the output voltage is regulated to track the reference input at refin pin. the reference input can be obtained from power input by voltage divider or from an independent voltage reference. a ceramic capacitor physically near the ic is required to filter the refernce voltage. output voltage and output capacitor, c out the up8809 is designed to work with low esr ceramic capacitors. no special concern is required on esr for stable operation. a minimum bulk capacitance of 10uf, along with a 0.1uf ceramic decoupling capacitor is recommended. increasing the bulk capacitance will improve the overall transient response. the use of multiple lower value ceramic capacitors in parallel to achieve the desired bulk capacitance will not cause stability issues. although designed for use with ceramic output capacitors, the up8809 is extremely tolerant of output capacitor esr values and thus will also work comfortably with tantalum output capacitors. t n e n o p m o ce u l a v d e d n e m m o c e r c t u o r o t i c a p a c c i m a r e c f u 0 1 m u m i n i m note: a 10uf ceramic capacitor is recommended, and actual stability is highly dependent on temperature and load conditions. insufficient capacitance may cause oscillation, while high equivalent series resistance (esr) exacerbates output voltage fluctuation under rapid load change conditions. total output capacitors value including ceramic and aluminum electrolytic capacitors should be larger than 10uf. thermal consideration the up8809 integrates internal thermal limiting function to protect the device from damage during fault conditions. however, continuously keeping the junction near the thermal shutdown temperature may remain possibility to affect device reliability. it is highly recommended to keep the junction temperature below the recommended operation condition 125 o c for maximum reliability. power dissipation in the device is calculated as: p d = (v in - v out ) x i out + v cntl x i cntl it is adequate to neglect power loss with respective to control circuit v cntl x i cntl when considering thermal management in up8809. take the following moderate operation condition as an example: v in = 2.5v, v out = 1.5v, i out = 1a, the power dissipation is: p d = (2.5v- 1.5v) x 1a = 1.0w this power dissipation is conducted through the package into the ambient environment, and, in the process, the temperature of the die (t j ) rises above ambient. large power dissipation may cause considerable temperature raise in the regulator in large dropout applications. the geometry of the package and of the printed circuit board (pcb) greatly influence how quickly the heat is transferred to the pcb and away from the chip. the most commonly used thermal metrics for ic packages are thermal resistance from the chip junction to the ambient air surrounding the package ( ja ): ja = ( t j -t a ) / p d
up8809 10 up8809-ds-f0000, jan. 2015 www.upi-semi.com ja specified in the thermal information section is measured in the natural convection at t a = 25 o c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the exposed pad for psop-8 package. given power dissipation p d , ambient temperature and thermal resistance ja , the junction temperature is calculated as: t j = t a + ? t ja = t a + p d x ja to limit the junction temperature within its maximum rating, the allowable maximum power dissipation is calculated as: p d(max) = ( t j(max) -t a ) / ja where t j(max) is the maximum operation junction temperature 125 o c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. ja of psop-8 packages is 75 o c/w on jedec 51-7 (4 layers, 2s2p) thermal test board with minimum copper area. the maximum power dissipation at t a = 25 o c can be calculated as: p d(max) = (125 o c - 25 o c) / 75 o c/w = 1.33w the thermal resistance ja highly depends on the pcb design. copper plane under the exposed pad is an effective heatsink and is useful for improving thermal conductivity. figure 3 shows the relationship between thermal resistance ja vs. copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 o c. a 50mm 2 copper plane reduces ja from 75 o c/w to 50 o c/w and increases maximum power dissipation from 1.33w to 2w. 60 7 0 50 40 30 20 10 0 60 70 50 40 30 90 100 80 thermal resistance ja ( o c/w) copper area (mm 2 ) figure 3. thermal resistance ja vs. copper area application information figure 4 illustrated the recommended pcb layout for best thermal performance. nc vin nc vcntl nc gnd refin vout gnd 1 2 3 45 6 7 8 figure 4. recommended pcb layout. layout consideration 1. place a local bypass capacitor as closed as possible to the vin pin. use short and wide traces to minimize parasitic resistance and inductance. 2. the exposed pad should be soldered on gnd plane with maximum area and with multiple vias to inner layer of ground place for improved thermal performance. 3. connect voltage divider directly to the point where regulation is required. place voltage divider close to the device.
up8809 11 up8809-ds-f0000, jan. 2015 www.upi-semi.com note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. package information psop-8 package 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.90 - 2.55 2.60 - 3.40 0.00 - 0.15 1.70 max 1
up8809 12 up8809-ds-f0000, jan. 2015 www.upi-semi.com package information 0.31 - 0.51 4.80 - 5.00 5.80 - 6.20 3.81 bsc 0.10 - 0.25 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.75 max fsop-8 package note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target. min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm.
up8809 13 up8809-ds-f0000, jan. 2015 www.upi-semi.com package information package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wdfn3x3-8l 1 4 58 0.18 - 0.30 0.50 bsc 2.90 - 3.10 2.90 - 3.10 1.40 - 1.80 0.30 - 0.50 2.00 - 2.50 0.00 - 0.05 0.20 ref 0.70 - 0.80
up8809 14 up8809-ds-f0000, jan. 2015 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2015, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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